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DIFFERENCE B/W DDR1 AND DDR2
DDR SDRAM or double-data-rate synchronous dynamic random access memory is a class of memory integrated circuit used in computers. It achieves greater bandwidth than the preceding single-data-rate SDRAM by transferring data on the rising and falling edges of the clock signal (double pumped).
Effectively, it nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM, the “SDR” being a retrospective designation.
With data being transferred 64 bits at a time DDR RAM gives a transfer rate of [mbcr x 2 x 64] / 8; annotated it looks like this: (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte).
Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a max transfer rate of 1600 MB/s. JEDEC has set standards for speeds of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules.
DDR2
In electronic engineering, double-data-rate two synchronous dynamic random access memory (DDR2 SDRAM) is a random access memory technology used for high speed storage of the working data of a computer or other digital electronic device.
It is a part of the SDRAM (synchronous dynamic random access memory) family of technologies, which is one of many DRAM (dynamic random access memory) implementations, and is an evolutionary improvement over its predecessor, DDR SDRAM (double-data-rate synchronous dynamic random access memory).
Its primary benefit is the ability to run its bus at twice the speed of the memory cells it contains, thus enabling faster bus speeds and higher peak throughputs than earlier technologies. This is achieved at the cost of higher latency.
Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling edge of the clock (a technique called double pumping). The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, so four words of data can be transferred per memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
Chip characteristics
DRAM density
Size of the chip in megabits. For example, 256 Mbit, or 32 MB chip. Nearly all motherboards only recognize 1 GB modules if they are low density 64M×8 modules. If high density 128M×4 1 GB modules are used, they most likely will not work. The JEDEC standard allows 128M×4 only for slower buffered/registered modules designed specifically for some servers, but some generic manufacturers do not comply.]
DRAM organization
Written in the form of 64M×4, where 64M is a number of storage units (64 million), x4 (pronounced “by 4″) — number of bits per chip, which equals the number of bits per storage unit. There are ×4, ×8, and ×16 DDR chips. The ×4 chips allow the use of advanced error correction features like Chip kill, memory scrubbing and Intel SDDC, while the ×8 and ×16 chips are somewhat more expensive.
Module characteristics
Capacity
Number of DRAM Devices
The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (single sided) or both sides (dual sided) of the module. The maximum number of chips per DDR module is 36 (9×4) for ECC and 32 (8×4) for non-ECC.
ECC vs non-ECC
Modules that have error correcting code are labeled as ECC. Modules without error correcting code are labeled non-ECC.
Number of DRAM Ranks
(also known as rows or sides) Any given module can have 1, 2, or 4 ranks, but only 1 rank of a module can be active at any moment in time. When a module has two or more ranks, the memory controller must periodically switch between them by performing close and open operations. Do not confuse rows in this context with rows used to describe internal chip architecture (that is why the term rank is to be preferred). The term sides is also confusing because it incorrectly suggests that this is tied to the physical placement of chips on the module.
Timings
CAS latency (CL), clock cycle time (tCK), row cycle time (tRC), refresh row cycle time (tRFC), row active time (tRAS).
Buffering
registered (or buffered) vs unbuffered
Packaging
Typically DIMM or SO-DIMM
Power consumption
Increases with clock rate
Module and chip characteristics are inherently linked.
Total module capacity is a product of one chip’s capacity by the number of chips. ECC modules multiply it by 8/9 because they use one bit per byte for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.
DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using ×8 chips instead of ×4 will have more ranks.
| Example: Variations of 1 GB PC2100 Registered DDR SDRAM module with ECC |
| Module size (GB) |
Number of chips |
Chip size (Mbit) |
Chip organization |
Number of rows (ranks) |
| 1 |
36 |
256 |
64M×4 |
2 |
| 1 |
18 |
512 |
64M×8 |
1 |
| 1 |
18 |
512 |
128M×4 |
1 |
This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single or dual ranked.
There is a common belief that number of module ranks or rows equals number of sides. As above data shows, this is not true. One can find 2-side/1-rank or 2-side/4-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it’s unlikely such a module was ever produced.
Double data rate (DDR) SDRAM specification
From JEDEC Board Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics.
Standard No. 79 Revision Log:
- Release 1, June 2000
- Release 2, May 2002
- Release C, March 2003 – JEDEC Standard No. 79C.
“This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well.”]
High density vs low density
High density memory here means non-ECC 184 pin SDRAM memory.
Organization
PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. As the memory is double pumped, this means that the effective clock rate of PC3200 memory is 400 MHz.
1 GB PC3200 non-ECC modules are usually made with sixteen 512 Mbit chips, 8 down each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized with 64 Mbits and a data width of 8 bits for each chip, commonly expressed as 64M×8. Memory manufactured in this way is low density RAM and will usually be compatible with any motherboard specifying PC3200 DDR-400 memory.
High density RAM
In the context of the 1 GB non-ECC PC3200 SDRAM module, there is very little visually to differentiate low density from high density RAM. High density DDR RAM modules will, like their low density counterparts, usually be double-sided with eight 512 Mbit chips per side. The difference is that for each chip, instead of being organized in a 64M×8 configuration, it is organized with 128 Mbits and a data width of 4 bits, or 128M×4. To further confuse the issue, some RAM is labeled as 128M×8, and is also called high density.
Most high density PC3200 modules are assembled using Samsung chips. These chips come in both the familiar 22 × 10 mm (approx.) TSOP2 and smaller squarer 12 × 9 mm (approx.) FBGA package sizes. High density Samsung chips can be identified by the numbers on each chip. If the sixth and seventh characters are 04 (for example K4H510438D-UCCC) then the chips are ×4 and high density. If the sixth and seventh characters are 08 then the chips are ×8 and low density.
High density RAM devices were designed to be used in registered memory modules for servers. As a result, performance or response times may suffer when used on a desktop or workstation. JEDEC standards do not apply to high-density DDR RAM in desktop implementations. JEDEC’s technical documentation, however, supports 128M×4 semiconductors as such that contradicts 128×4 being classified as high density. As such, high density is a relative term, which can be used to describe memory which is not supported by a particular motherboard’s memory controller.
Alternatives
Comparison of DDR, DDR2 and DDR3 for Desktop PCs
| DDR SDRAM Standard |
Frequency (MHz) |
Voltage[10] |
| DDR |
100–200 |
2.5/2.6 |
| DDR2 |
200–533 |
1.8 |
| DDR3 |
400–800 |
1.5 |
DDR (DDR1) has been superseded by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are Rambus XDR DRAM. DDR2 has become the standard, as XDR is lacking support. DDR3 SDRAM is a new standard that offers even higher performance and new features.
DDR’s prefetch buffer depth is 2 bits, while DDR2 uses 4 bits. Although the effective clock rates of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.[11]
Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR1 leaves off, and is available at clock rates of 400 MHz and higher. RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets. DDR1 memory’s prices have substantially increased since Q2 2008 while DDR2 prices are reaching an all-time low. In January 2009, 1 GB DDR1 is 2–3 times more expensive than 1 GB DDR2. High density DDR RAM will suit about 10% of PC motherboards on the market while low density will suit almost all
So; this is all I know about DDR1 and DDr2..I hope it will be helpful to you
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